DEVICE	SX48,osc4mhz
		RESET	main
		FREQ 4_000_000

; define symbols

		foo		EQU	$0a
		channel		EQU	$0d
		value		EQU	$0e
		counter		EQU	$0f
		rtcc_offset	EQU	$d4


;;;;;;;;;;;;;;; interrupt handler
		org 0
		
		mov     m, #$09			; Set up to write wake up pending register
		clr     w
		mov     !rb, w			; Read WKPND_B register content and clear it after that

		and	w, #$1
		jz	isr_timer		; not a hardware interrupt

		mov	w, rb			; only sync on rising edges
		and	w, #$1
		jz	falling_edge

rising_edge
		mov     !OPTION, #%11010000	; disable timer interrupts
		mov     rc, #$0			; reset all pins
		mov     rd, #$0			; reset all pins

		; now copy all values vom $2x to $1x
		bank	$20
		mov	w, $20
		bank	$10
		mov	$10, w

		bank	$20
		mov	w, $21
		bank	$10
		mov	$11, w

		bank	$20
		mov	w, $22
		bank	$10
		mov	$12, w

		bank	$20
		mov	w, $23
		bank	$10
		mov	$13, w

		bank	$20
		mov	w, $24
		bank	$10
		mov	$14, w

		bank	$20
		mov	w, $25
		bank	$10
		mov	$15, w

		bank	$20
		mov	w, $26
		bank	$10
		mov	$16, w

		bank	$20
		mov	w, $27
		bank	$10
		mov	$17, w

		bank	$20
		mov	w, $28
		bank	$10
		mov	$18, w

		bank	$20
		mov	w, $29
		bank	$10
		mov	$19, w

		bank	$20
		mov	w, $2a
		bank	$10
		mov	$1a, w

		bank	$20
		mov	w, $2b
		bank	$10
		mov	$1b, w

		bank	$20
		mov	w, $2c
		bank	$10
		mov	$1c, w

		bank	$20
		mov	w, $2d
		bank	$10
		mov	$1d, w

		bank	$20
		mov	w, $2e
		bank	$10
		mov	$1e, w

		bank	$20
		mov	w, $2f
		bank	$10
		mov	$1f, w

		reti

falling_edge
		clr	counter
		clr	rtcc
		mov     !OPTION, #%10010000	; enable timer interrupts
		reti

isr_timer
		bank 	$10
		mov	foo, rc

chn0
		mov 	w, $10
		xor 	w, counter
		jnz 	chn0_skip
		setb	foo.0
		jmp	chn1
chn0_skip
		nop
		nop
		nop
		nop
chn1
		mov 	w, $11
		xor 	w, counter
		jnz 	chn1_skip
		setb	foo.1
		jmp	chn2
chn1_skip
		nop
		nop
		nop
		nop
chn2		
		mov 	w, $12
		xor 	w, counter
		jnz 	chn2_skip
		setb	foo.2
		jmp	chn3
chn2_skip
		nop
		nop
		nop
		nop
chn3
		mov 	w, $13
		xor 	w, counter
		jnz 	chn3_skip
		setb	foo.3
		jmp	chn4
chn3_skip
		nop
		nop
		nop
		nop
chn4
		mov 	w, $14
		xor 	w, counter
		jnz 	chn4_skip
		setb	foo.4
		jmp	chn5
chn4_skip
		nop
		nop
		nop
		nop
chn5
		mov 	w, $15
		xor 	w, counter
		jnz 	chn5_skip
		setb	foo.5
		jmp	chn6
chn5_skip
		nop
		nop
		nop
		nop
chn6
		mov 	w, $16
		xor 	w, counter
		jnz 	chn6_skip
		setb	foo.6
		jmp	chn7
chn6_skip
		nop
		nop
		nop
		nop								
chn7
		mov 	w, $17
		xor 	w, counter
		jnz 	chn7_skip
		setb	foo.7
		jmp	chn8
chn7_skip
		nop
		nop
		nop
		nop
chn8
		mov	rc, foo
		mov	foo, rd

		mov 	w, $18
		xor 	w, counter
		jnz 	chn8_skip
		setb	foo.0
		jmp	chn9
chn8_skip
		nop
		nop
		nop
		nop
chn9
		mov 	w, $19
		xor 	w, counter
		jnz 	chn9_skip
		setb	foo.1
		jmp	chn10
chn9_skip
		nop
		nop
		nop
		nop
chn10
		mov 	w, $1a
		xor 	w, counter
		jnz 	chn10_skip
		setb	foo.2
		jmp	chn11
chn10_skip
		nop
		nop
		nop
		nop
chn11
		mov 	w, $1b
		xor 	w, counter
		jnz 	chn11_skip
		setb	foo.3
		jmp	chn12
chn11_skip
		nop
		nop
		nop
		nop
chn12
		mov 	w, $1c
		xor 	w, counter
		jnz 	chn12_skip
		setb	foo.4
		jmp	chn13
chn12_skip
		nop
		nop
		nop
		nop
chn13
		mov 	w, $1d
		xor 	w, counter
		jnz 	chn13_skip
		setb	foo.5
		jmp	chn14
chn13_skip
		nop
		nop
		nop
		nop
chn14
		mov 	w, $1e
		xor 	w, counter
		jnz	chn14_skip
		setb	foo.6
		jmp	chn15
chn14_skip
		nop
		nop
		nop
		nop
chn15
		mov 	w, $1f
		xor 	w, counter
		jnz 	chn15_skip
		setb	foo.7
		jmp	isr_exit
chn15_skip
		nop
		nop
		nop
		nop

isr_exit
		mov	rd, foo

		inc 	counter
		mov	rtcc, #rtcc_offset
		reti

;;;;;;;;;;;;;;; end of interrupt handler


;;;;;;;;;;;;;;; main routine

main		mov	w, #$1f
		mov	m, w
		mov	ra, #%0001		; set port A output latch initial state
		mov	!ra,#%1100		; port A input/output direction
		mov	!rb,#%00000001		; port B to output direction
		mov	!rc,#%00000000		; port C to output direction
		mov	!rd,#%00000000		; port D to output direction
		mov	!re,#%11111111		; port E to input direction

		mov 	m, #$09			; set up to write wake up pending register 
		clr 	w 
		mov 	!rb, w			; read WKPND_B register content and clear it after that
		
		mov     m, #$0A
		mov	w, #%11111110
		mov	!rb, w			; rising edges

		mov	m, #$0B
		mov	w, #%11111110
		mov	!rb, w			; enable hardware interrupt on pin 0


; inital values
;		bank	$10
;		mov	$10, #100

loop
		jnb	ra.3, rxdata		; if no data do nothing
		jmp 	loop

rxdata
		clrb	ra.0			; enable read from 245
		nop				; allow time for data to settle
		nop
		mov	w, re			; move data from 245 to W
		mov	channel, w		; move W to channel register
		setb	ra.0			; disable read from 245
		nop
		nop

getdata
		jnb	ra.3, gotdata		; Check for data in RX buffer
		jmp	getdata			; if no data do nothing
gotdata
		clrb	ra.0			; enable read from 245
		nop
		nop
		mov	w, re			; move data from 245 to W
		mov	value, w
		setb	ra.0			; disable read from 245
		nop
		nop

		and	w, #%10000000
		jnz	loop

		xor	w, #%01111111
		jz	loop

		mov	w, channel
		and	w, #%10000000
		jz	loop
		sub	channel, w

		mov	w, channel		; choose type of channel to set
		and	w, #%11110000
		jnz	upper_chns

lower_chns					; lower channels, 0-15, can be set in 128 steps
		bank	$20
		mov	w, channel		; indirect addressing voodoo
		mov	FSR, w
		mov	w, #$20			; add $10 to channel value
		add	FSR, w
		mov	INDF, value
		nop
		nop
		jmp 	loop

upper_chns					; all other channel mean the upper 4 ones (on/off)
		rr	value
		rr	value
		rr	value
		rr	value
		rr	value
		mov	rb, value

		jmp	loop